This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 10-319158, filed Nov. 10, 1998, the entire contents of which are incorporated herein by reference.
The present invention relates to a matrix switch, which is suitable for applying to a node (transmission equipment) in a ring network and comprises a function to connect a plurality of digital signal input lines with an arbitrary line of a plurality of output lines.
In the ring network, which is constructed by using an optical cable, the matrix switch, which connects the plurality of digital signal input lines with an arbitrary line of the plurality of output lines, is provided in add-drop multiplexer (ADM), which is the transmission equipment constructing each node.
This conventional kind of matrix switch achieves nxc3x97m matrix switch by comprising m selection blocks to select one line from n input lines (#1 to #n) as shown in FIG. 1. That is, the input data to the matrix switch block is directly branched and is connected with each selection block, and the input data specified according to input data selection control signals (1 to m) from the outside equipment is selected and is output, conventionally.
In the conventional configuration as described above, the I/O signals of the matrix switch block increases and the circuit scale becomes huge, too, when the scale of the matrix switch becomes large. Therefore, it is necessary to input and output all of the signals, which are input and output from/to the matrix switch blocks, to one matrix switch block, when it is achieved as an equipment. Therefore, there is a disadvantage of a very difficult achievement caused by a physical restriction in the number of pins of connectors and the circuit mounting in the printed circuit board or modules of matrix switch blocks.
It is possible to apply the multistep connection configuration with a plurality of small-scale matrix switches by dividing the matrix switch block to solve this physical disadvantage. Though the number of I/O signals of one matrix switch and the circuit scale is decreased in this configuration, there is the disadvantage that the control algorithm of the entire matrix switch block becomes complex. That is, even if the input block and the output block of the matrix switch are the same parts, for example, the plurality of routes can be selected.
As described above, in the conventional matrix switch configuration, since nxc3x97m matrix switch is achieved by comprising m selection blocks to select one line among n input lines, the number of the I/O signals of the matrix switch block increases and the circuit scale becomes huge, too when the scale of the matrix switch becomes large, and it is necessary to input and output all of the signals, which are input and output from/to the matrix switch block, from/to one matrix switch block when it is achieved as an equipment. Therefore, there is a disadvantage at a very difficult achievement caused by a physical restriction in the number of pins of connectors and the circuit mounting in the printed circuit board or the module of matrix switch blocks. To solve this physical disadvantage, the number of I/O signals of one matrix switch and the circuit scale are decreased when applying the multistep connection configuration with a plurality of small-scale matrix switches by dividing the matrix switch block, but there is a disadvantage that the control algorithm of the entire matrix switch block becomes complex.
An object of the present invention is to provide a matrix switch in which the number of data lines input and output from/to a matrix switch block is decreased, function block division is easy when it is achieved as an equipment, in addition, complex communication path setting algorithm is not required even if the matrix switch block is divided and control of the matrix switch block is possible by the same algorithm as existing configuration.
The matrix switch according to the present invention characterized by comprising a matrix switch main body, a preprocessing block provided on an input side of the matrix switch main body, and a postprocessing block provided on an output side of the matrix switch main body, in which each of the preprocessing block, the matrix switch main body and the postprocessing block comprises a circuit, which parallel-converts a line input with each setting bit width, performs a bit stream operation in the setting bit width, serial-converts it, and performs line output, respectively, and the matrix switch main body is divided into the setting bit width parallel-converted with the preprocessing block and switching-control is performed. In other words, the matrix switch according to the present invention is characterized in that a line input is parallel-converted with a predetermined bit width, and a selection processing is performed with a plurality of matrix switch main bodies having a width corresponding to each of plurality of bit widths, thereafter a serial conversion is performed and a serial-converted signal is output.
More specifically, a matrix switch according to the present invention, is comprising: a preprocessing block having j preprocessing basic blocks (n=ixc3x97j: where, n, i, j, and k are natural numbers), wherein a block including n first parallel conversion blocks, which perform i-bit parallel conversion of bit serial data of each of n input lines, and an i first multiplex blocks, which multiplex a k-th bit (1xe2x89xa6kxe2x89xa6i) of data, which performs i-bit parallel conversion with the first parallel conversion block for i input lines, are assumed to be one of the preprocessing basic blocks; a matrix switch block having i matrix switch basic blocks (where, m and q are natural numbers), wherein j second parallel conversion blocks, which performs i-bit parallel conversion of the data of the j input lines processed by the preprocessing block, m selection blocks, which selects one data from ixc3x97j data in which i-bit parallel conversion is performed with the second parallel conversion block, and q second multiplex blocks, which multiplex i-lines of the data selected with the selection block, are assumed to be one of the matrix switch basic blocks; and a postprocessing block having p postprocessing basic blocks (m=ixc3x97q), wherein the third parallel conversion block, which performs i-bit parallel conversion of qxc3x97i data output from the matrix switch block, and a third multiplex block, which multiplexes i input lines of k-th bit of data in which i-bit parallel conversion is performed with the third parallel conversion block are assumed to be one of the postprocessing basic blocks.
The preferred manners are as follows in the above-mentioned each matrix switch.
(1) The preprocessing block comprises an elastic buffer to an input terminal thereof.
(2) The matrix switch block comprises an elastic buffer to an input terminal thereof.
(3) The postprocessing block comprises an elastic buffer to an input terminal thereof.
(4). The preprocessing block comprises a first monitor block, which monitors an input data and a first P-AIS insertion block, which inserts a P-AIS signal into the input data when abnormality of the input data is detected by the first monitor block, at a previous stage of the first parallel conversion block, the matrix switch block comprises a second monitor block, which monitors an input data and a fixed data insertion block, which inserts fixed data into the input data when abnormality of input data is detected by the second monitor block, at a previous stage of the second parallel conversion block, and the postprocessing block comprises a third monitor block, which is provided at a previous stage of the third parallel conversion block and monitors an input data, a fourth monitor block, which is provided at a latter stage of the third parallel conversion block and detects a fixed data inserted by the fixed data insertion block, a first logical sum block, which outputs a logical sum of outputs from the third monitor block, a second logical sum block, which outputs a logical sum of outputs from the first logical sum block and the fourth monitor block, and a P-AIS insertion block, which inserts a P-AIS signal into an output signal from the third monitor block according to the output from the second logical sum block.
According to the matrix switch according to the present invention, the number of the data lines input and output from/to the matrix switch main body (matrix switch block) is decreased by a parallel/serial conversion with the preprocessing block, the matrix switch block, and the postprocessing block, and the matrix switch main body (matrix switch block) having a width corresponding to the parallel bit width parallel-converted by the preprocessing block performs a division processing. Therefore, the function block division becomes easy when it is achieved as an equipment. In addition, a complex communication path setting algorithm is not required even when the matrix switch main body (matrix switch block) is divided, and it becomes possible to control the matrix switch main body (matrix switch block) by the same algorithm as a conventional configuration. In addition, when the bit rate of the I/O data rises, the selection block of the matrix switch main body (matrix switch block) also has the advantage of enabling a low-speed processing.
As described above, according to the present invention, the following matrix switch can be provided, that is, the number of the data input and output from/to the matrix switch block can be decreased, the function block division is easy when it is achieved as a equipment, and, in addition, the switch scale can be easily expanded without request of a complex communication path setting algorithm even when the matrix switch block is divided, and the matrix switch block can be controlled by the same algorithm as an existing configuration. When the bit rate of the I/O data rises, the selection block of the matrix switch block (switch main body) also has the advantage of enabling a low-speed processing. In addition, when the phase shift by wiring the cable between each of blocks, etc. are considered, an operation with high reliability can be secured by further relaxing the restriction in the specification by arranging the elastic buffer at one of or all of the input terminals of the preprocessing block, the input terminal of the matrix switch block, or the input terminal of the postprocessing block, and constructing to perform processing after all of the frame phases of input data are coincide.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.